1. Field of the Invention
The present invention relates to level shifting circuits for generating a high voltage domain output signal responsive to a low voltage domain input signal.
2. Description of the Related Art
Level shifting circuits are commonly used to convert a signal from a low voltage domain to a high voltage domain. For example, a logic signal may be generated by circuitry which is powered by a low-voltage power supply voltage, such as VDD (e.g., 1.5 volts), and thus have output levels generally corresponding to VDD and ground. However many circuits, such as programmable memory devices, utilize higher voltages for internal signals in programming and erase modes than in a read mode. Frequently such devices use an internal power supply voltage from 3-10 volts or higher, which may be known as VPP. Consequently, it is useful to generate level shifted “versions” of these low-level logic signals, which level shifted signals have output levels of VPP and ground, to provide appropriate voltages on various switched circuit nodes, especially during programming and erase modes of operation.
As semiconductor devices have become smaller, the voltage which may be safely applied across various devices has decreased. For example, the maximum voltage that may be safely applied from drain to source terminals of a non-conducting N-channel MOSFET transistor (i.e., an “off” NMOS transistor) is frequently known as a breakdown voltage. However, when such a transistor is conducting, the maximum voltage that may be safely applied from drain to source terminals is frequently a lower voltage than the breakdown voltage. Such a voltage is known as the “snap back” voltage, which is named for the visual appearance of the transistor's I-V curve when subjected to such conditions.
Snap back concerns frequently limit the operating voltage achievable in a level shifting circuit, and may pose significant reliability concerns in such level shifting circuits. Snap back problems are more problematic in NMOS devices than in PMOS devices, because of the greater susceptibility of electrons being trapped in oxides and surface traps than the susceptibility for holes being trapped. Snap back can cause catastrophic failure of a device, and hence the failure of a circuit incorporating such a device. Consequently, snap back problems are more likely to arise in sub-circuits used to discharge a high voltage node, such as an output node of a level shifter circuit.
Referring now to FIG. 1, a snapback protected level shifter 100 is shown. A logic signal DIN is conveyed on node 102, and is the input signal for this level shifter 100. This input signal need not correspond to a “data” signal, but can be any logic signal, such as an address signal, a decoded or pre-decoded address signal, a control signal, or any other logic signal generally having one of two logic states for a low-voltage domain as its signal levels. The inverters 103, 105, 107, 108, and 109 all belong to this low-voltage domain, being powered by VDD (node 143) and ground (node 140), and thus the signals generated on nodes 104, 106 128, and 129 are each “VDD-level” signals (i.e., having a “high” level of VDD, and a “low” level of ground). These low-voltage inverters 103, 105, 107, 108, and 109 are implemented with low-voltage transistors having a typical threshold voltage (VT) of 300-600 mV, and which devices are not suitable to connection to high voltage nodes.
A second power supply VPP is conveyed on node 145. Such a power supply may be provided from an external source, or may be generated internally within the overall circuit (e.g., a FLASH memory device or other programmable memory device). Moreover, the voltage conveyed on the VPP node 145 may vary depending upon the mode of operation. For example, the magnitude of the VPP voltage in a read mode may be much lower (e.g., 3 volts) than in a write, programming, or erase mode. For the description that follows, we shall assume the VPP voltage to be a high voltage (e.g., 10 volts, such as for a programming mode) well above the snap back voltage for typical NMOS transistors.
The complementary XQ, Q output nodes 114, 115 are coupled to VPP by cross-coupled PMOS transistors 120, 121, and are coupled to ground by matching discharge circuits. The XQ output node 114 is discharged by native transistors 122, 130, 132, and the output pull down transistor within inverter 103, all as described below. Similarly, the Q output node 115 is discharged by native transistors 123, 131, 133, and the output pull down transistor within inverter 105. Such native transistors usually have a threshold voltage near zero volts.
High voltage NMOS devices may be available in some semiconductor processes. However, a suitable high voltage device for 10 volt operation likely requires a threshold voltage high enough (e.g., VT=600-1200 mV) that a VDD level signal on its gate (e.g., as low as 1.2 volts) would barely turn on such a device, if at all.
To understand the operation of this circuit, assume initially that the DIN signal is high (i.e., VDD), and that consequently the Q output node 115 is also high (i.e., VPP) and that the XQ output node 114 is low (i.e., ground). Next assume that the DIN node transitions from a high to a low level (i.e., from VDD to ground). Clearly the intended operation is to bring the voltage of the Q output node 115 to ground, and to bring the voltage of the XQ output node 114 to VPP. With DIN at ground, node 128 is brought to ground, transistor 130 is turned off, and the XQ output node 114 is free to be driven high by PMOS transistor 120 when turned on by the decreasing voltage on the Q output node 115 that is coupled to the gate of transistor 120 (described in detail below).
With DIN at ground, node 106 is also driven to ground, and node 129 is driven high (i.e., VDD) by inverter 109. However, since transistor 131 is very sensitive to snap back, the rise time of node 129 is intentionally slowed so that the gate-to-source voltage of transistor 131 develops very slowly, and thus transistor 131 turns on very slowly, to thereby discharge node 127 (i.e., reducing the drain-to-source voltage on transistor 131) before the gate-to-source voltage of transistor 131 reaches a voltage that would cause a snap back condition. Such intentional slowing may be accomplished by using transistors in inverter 109 that have a longer electrical length than the usual “minimum length” transistors for a given semiconductor process. The level shift diode 123 is provided to decrease the voltage on node 127 to a lesser value than the voltage of the Q output node 115, to reduce the voltage otherwise impressed across transistor 131. As the voltage of node 129 continues to rise, and as the voltage of node 127 continues to fall, transistor 133 will eventually turn on, bypassing the level shift diode 123, and providing a discharge path from the Q output node 115, through transistor 133, transistor 131, and the inverter 105 pull down transistor, to ground. This discharge path is suitable to drive the Q output node 115 fully to ground, without resulting in a low level that “rides” above ground by a diode drop.
As the Q output 115 is being discharged, the PMOS pull-up transistor 121 initially remains fully turned on until the voltage of the Q output node 115 is reduced by at least a PMOS threshold voltage (VT) so that PMOS transistor 120 turns on, charging up the complementary XQ output node 114, and turning off PMOS transistor 121 to thereby allow the discharge path to completely discharge the Q output node 115, and to achieve a quiescent state with no standby power dissipation. Such intentionally weakened pull down paths require that the corresponding pull up paths must also be weakened. In other words, if the discharge path is weakened, the pull-up path must also be weakened if the voltage on the output node is able to be reduced by at least a PMOS threshold voltage.
The weakened drive strength in both the charging (i.e., pull-up) path and the discharging (i.e., pull-down) path increases the delay through such a level shifter circuit, and thus reduces circuit performance. Moreover, the various transistors in the level shifter circuit must be sized for a given output load. As a result, no standard-sized level shifter circuit may be used with varying output capacitive loading without risking the reliability of the level shifter circuit.
Considerable efforts have been applied in the art to design around such snap back concerns, which sometimes results in circuits having unusually high complexity to accomplish what might seem like a simple logic structure. Nonetheless, improvements in such level shifter circuits are always beneficial.